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OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54 / 74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.
SN54/74LS373 SN54/74LS374
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT
LOW POWER SCHOTTKY
20 1
J SUFFIX CERAMIC CASE 732-03
* * * * * * *
Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Hysteresis on Latch Enable Edge-Triggered D-Type Inputs Buffered Positive Edge-Triggered Clock Hysteresis on Clock Input to Improve Noise Margin Input Clamp Diodes Limit High Speed Termination Effects
LOADING (Note a)
20 1
N SUFFIX PLASTIC CASE 738-03
PIN NAMES
20
HIGH D0 - D7 LE CP OE O0 - O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L.
LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L.
DW SUFFIX SOIC CASE 751D-03
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC
NOTES: a) 1 TTL Units Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25 U.L. for Commercial (74) Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for Commercial (74) Temperature Ranges.
CONNECTION DIAGRAM DIP (TOP VIEW) SN54 / 74LS373
VCC O7 20 19 D7 18 D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 LE 11 VCC O7 20 19 D7 18
SN54 / 74LS374
D6 17 O6 16 O5 15 D5 14 D4 13 O4 12 CP 11
1 OE
2 O0
3 D0
4 D1
5 O1
6 O2
7 D2
8 D3
9 O3
10 GND
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
1 OE
2 O0
3 D0
4 D1
5 O1
6 O2
7 D2
8 D3
9 O3
10 GND
FAST AND LS TTL DATA 5-1
SN54/74LS373 * SN54/74LS374
TRUTH TABLE LS373
Dn H L X X LE H H L X OE L L L H On H L Q0 Z* Dn H L X X
LS374
LE OE L L H On H L Z*
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance * Note: Contents of flip-flops unaffected by the state of the Output Enable input (OE).
LOGIC DIAGRAMS SN54LS / 74LS373
3 4 7 8 13 14 17 18
D0 D LATCH ENABLE LE 11 OE Q G
D1 D Q G
D2 D Q G
D3 D Q G
D4 D Q G
D5 D Q G
D6 D Q G
D7 D Q G
VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
1
O0
2 5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
SN54LS / 74LS374
3 11 4 7 8 13 14 17 18
D0 CP D QQ CP D QQ
D1 CP D QQ
D2 CP D QQ
D3 CP D QQ
D4 CP D QQ
D5 CP D QQ
D6 CP D QQ
D7
CP
OE
1 2
O0
5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 1.0 - 2.6 12 24 Unit V C mA mA
FAST AND LS TTL DATA 5-2
SN54/74LS373 * SN54/74LS374
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL IOZH IOZL IIH IIL IOS ICC Output LOW Voltage 74 Output Off Current HIGH Output Off Current LOW Input HIGH Current Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 30 0.35 0.5 20 - 20 20 0.1 - 0.4 - 130 40 V A A A mA mA mA mA 2.4 2.4 54 74 - 0.65 3.4 3.1 0.25 0.4 Min 2.0 0.7 0.8 - 1.5 Typ Max Unit Ui V V V V V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 12 mA IOL = 24 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VOUT = 2.7 V VCC = MAX, VOUT = 0.4 V VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits LS373 Symbol S bl fMAX tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter P Maximum Clock Frequency Propagation Delay, Data to Output Clock or Enable to Output Output Enable Time Output Disable Time 12 12 20 18 15 25 12 15 18 18 30 30 28 36 20 25 15 19 20 21 12 15 28 28 28 28 20 25 Min Typ Max Min 35 LS374 Typ 50 Max Unit Ui MHz ns ns ns ns CL = 5.0 pF CL = 45 pF, pF F RL = 667 Test C di i T Conditions
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits LS373 Symbol S bl tW ts th Clock Pulse Width Setup Time Hold Time Parameter P Min 15 5.0 20 Max Min 15 20 0 LS374 Max Unit Ui ns ns ns
DEFINITION OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to LE transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the LE transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition.
FAST AND LS TTL DATA 5-3
SN54/74LS373
AC WAVEFORMS
tW LE 1.3 V ts Dn tPLH OUTPUT tPHL th tW
Figure 1
OE tPZL VOUT 1.3 V 0.5 V 1.3 V 1.3 V tPLZ 1.3 V VOL OE tPZH VOUT 1.3 V 1.3 V tPHZ 1.3 V VOH 1.3 V 0.5 V
Figure 2
Figure 3
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5.0 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 4
FAST AND LS TTL DATA 5-4
SN54/74LS374
AC WAVEFORMS
tWH CP 1.3 V ts Dn tPLH OUTPUT 1.3 V 1.3 V tPHL 1.3 V tWL 1.3 V OE tPZL VOUT 1.3 V 0.5 V
1.3 V th
1.3 V
1.3 V tPLZ 1.3 V VOL
Figure 6
Figure 5
OE tPZH VOUT
1.3 V tPHZ 1.3 V
1.3 V VOH 1.3 V 0.5 V
Figure 7
AC LOAD CIRCUIT
VCC
SWITCH POSITIONS
RL SW1 SYMBOL tPZH tPZL TO OUTPUT UNDER TEST tPLZ tPHZ SW1 Open Closed Closed Closed SW2 Closed Open Closed Closed
5.0 k CL* SW2
* Includes Jig and Probe Capacitance.
Figure 8
FAST AND LS TTL DATA 5-5

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